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- W2000313478 abstract "Optimum Power gating sleep transistor design and implementation are critical to a successful low-power design. The large magnitude of supply and ground bounces, which arise from power mode transitions in large power gating structures results in wrong functioning of the circuit. We propose a novel power gating technique showing the trade-off between wake-up time and supply noise. This technique is simulated for a dual-core processor for 32nm CMOS technology and the supply rail noise is reduced to 1.35 mV." @default.
- W2000313478 created "2016-06-24" @default.
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- W2000313478 date "2010-12-01" @default.
- W2000313478 modified "2023-09-27" @default.
- W2000313478 title "Power Rail Noise Minimization during Mode Transition in a Dual Core Processor" @default.
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- W2000313478 doi "https://doi.org/10.1109/act.2010.26" @default.
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