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- W2000367626 abstract "The problem of the efficient realization of an adaptive digital linear prediction filter is investigated, and three implementation approaches are examined: a single-chip general-purpose digital signal processor realization, a multi-chip, multiplexed architecture, and a multichip systolic array approach. In addition, the complete architecture and organization of a systolic-type realization is also presented. A single-chip lattice stage of the systolic architecture contains both the filtering section and the adaptation logic which is based on the stochastic gradient adaptation algorithm. The filter-stage architecture uses bit-serial arithmetic by employing five bit-serial multipliers and four single-bit adders integrated on a single chip. Chips can be cascaded to obtain multiple-stage filters. The filter architecture is designed to operate with 17-bit, two's complement, fixed-point data with 16-bit precision. At an estimated 8.5-MHz clock rate, the chip could accommodate applications with data sampling rates of 500 KHz." @default.
- W2000367626 created "2016-06-24" @default.
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- W2000367626 date "1987-07-01" @default.
- W2000367626 modified "2023-09-25" @default.
- W2000367626 title "Design alternatives for adaptive digital lattice filters and a new bit-serial architecture" @default.
- W2000367626 doi "https://doi.org/10.1109/tcs.1987.1086199" @default.
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