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• W2000663326 abstract "Traditionally, we expect that circuit designs can be executed without errors. However, for error resilient applications such as image processing, 100% correctness is not necessary. By pursuing less than 100% correctness, power consumption can be significantly reduced. Recently, probabilistic CMOS and probabilistic Boolean circuits (PBCs) have been proposed to deal with power consumption issue. However, to the best of our knowledge, no correctness analysis and power optimization algorithms have been proposed for PBCs. Thus, in this paper, we first propose a statistical approach for evaluating the correctness of PBCs. Then, we propose strategies for power optimization of PBCs. Finally, we integrate these strategies with the correctness analysis as a power optimization algorithm for PBCs. The experimental results show that the proposed correctness analysis method is highly efficient and accurate, and that the power optimization algorithm saves 36% of total power-delay-product on average under a correctness constraint of 90% on a set of International Workshop on Logic and Synthesis (IWLS) 2005 benchmarks." @default.
• W2000663326 created "2016-06-24" @default.
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• W2000663326 date "2015-04-01" @default.
• W2000663326 modified "2023-10-17" @default.
• W2000663326 title "Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits" @default.
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• W2000663326 doi "https://doi.org/10.1109/tcad.2015.2394378" @default.
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