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• W2000675952 abstract "This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and 0.124 mum <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>inv</sub> scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> cell to meet low power application requirements." @default.
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• W2000675952 date "2008-12-01" @default.
• W2000675952 modified "2023-09-26" @default.
• W2000675952 title "Scaling of 32nm low power SRAM with high-K metal gate" @default.
• W2000675952 cites W2172203429 @default.
• W2000675952 doi "https://doi.org/10.1109/iedm.2008.4796660" @default.
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