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- W2000764516 abstract "10-b resolution is achieved by applying the existing commutated feed-back capacitor switching (CFCS) technique. Capacitive loads in the transfer characteristics are reduced in critical pipeline stages, and single-phase latches are proposed to reduce the number of delay elements by half. In order to obtain the required clock driving capability, distributed clock generator is used. This prototype is made into a 10-b 100-MS/s CMOS pipelined analog-to-digital converter (ADC) using 0.18 μ m CMOS 1P6M process. It dissipates 90 mW with a supply voltage of 1.8 V and occupies 0.98mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> active area. The measured performance achieves 56.2 dB signal to noise plus distortion ratio (SNDR) at sampling rate of 100 MS/s. The differential nonlinearity (DNL) and integral-nonlinearity (INL) are 0.54-LSB and 1.08-LSB, respectively." @default.
- W2000764516 created "2016-06-24" @default.
- W2000764516 creator A5007547590 @default.
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- W2000764516 date "2007-01-01" @default.
- W2000764516 modified "2023-09-27" @default.
- W2000764516 title "A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology" @default.
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- W2000764516 doi "https://doi.org/10.1109/socc.2007.4545413" @default.
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