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- W200076699 abstract "Current cell-based design methodology is limited by the set of standard cells available in the library. Optimization is limited by the coarse granularity of drive strengths and lack of skewed drive strength in libraries. Including these variants would lead to a huge library set, which would very quickly become unmanageable. Moreover, gate-level timing data are more conservative than transistor level timing due to guard banding during cell characterization. Optimizing the cells in their context at the transistor level removes these limitations." @default.
- W200076699 created "2016-06-24" @default.
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- W200076699 date "2005-12-29" @default.
- W200076699 modified "2023-09-23" @default.
- W200076699 title "Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing" @default.
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- W200076699 doi "https://doi.org/10.1007/0-306-47823-4_9" @default.
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