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- W2000816201 abstract "A buried stacked capacitor cell (BSCC), one of the most suitable cell structures for 16-Mb DRAMs (dynamic random-access memories), suffers from two kinds of unfavorable current leakage paths: between the storage node and the substrate, caused by the gate controlled diode structure along the trench sidewall SiO/sub 2/; and between the neighboring cell contacts, caused by the punchthrough under the field SiO/sub 2/. To improve these problems, a BSCC with ion implantation through the field SiO/sub 2/ (ITF-BSCC) is reported. The key feature is a p/sup +/ region that is formed 0.4-0.6 mu m from the Si substrate surface under the active region and isolation region. This p/sup +/ region acts as isolation under the field SiO/sub 2/ and as a potential barrier for the leakage current of the gate-controlled diode. This p/sup +/ region can be fabricated by boron ion implantation at 180-200 keV to a total dose of 5E11-1E12 cm/sup -2/. All steps of the processing except this boron ion implantation are the same as those of conventional BSCC. This leakage current of the gate-controlled diode with trenches fabricated by ITF-BSCC process and conventional BSCC process were measured. The peak leakage current of ITF-BSCC is 3-5 times lower than that of conventional BSCC.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2000816201 date "1988-01-01" @default.
- W2000816201 modified "2023-09-26" @default.
- W2000816201 title "ITF-BSCC technology for 16 Mbit DRAM cell" @default.
- W2000816201 doi "https://doi.org/10.1109/16.8840" @default.
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