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• W2000922050 abstract "This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21V and 0.26V, respectively, with a bit error rate of 10-8 kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell." @default.
• W2000922050 created "2016-06-24" @default.
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• W2000922050 date "2009-01-01" @default.
• W2000922050 modified "2023-09-27" @default.
• W2000922050 title "A Dependable SRAM with 7T/14T Memory Cells" @default.
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• W2000922050 doi "https://doi.org/10.1587/transele.e92.c.423" @default.
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