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• W2000928382 abstract "Various high-speed techniques have been developed for multipliers, but with the increasing popularity of mobile computing, a recent goal has been to minimize power dissipation. A popular delay-reduction technique applied to adder circuits is polarity inversion of bits. As this optimization reduces transistor count, it also has the potential for lowering power dissipation, and can be effectively applied to Wallace tree partial product reduction stages. We illustrate how this technique reduces power, interconnect capacitance, and chip area. Power reduction of up to 25% is achieved." @default.
• W2000928382 created "2016-06-24" @default.
• W2000928382 creator A5008408555 @default.
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• W2000928382 date "1999-01-01" @default.
• W2000928382 modified "2023-09-26" @default.
• W2000928382 title "Inverse polarity techniques for high-speed/low-power multipliers" @default.
• W2000928382 cites W2052373731 @default.
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• W2000928382 doi "https://doi.org/10.1145/313817.313942" @default.
• W2000928382 hasPublicationYear "1999" @default.
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