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- W2000966589 abstract "Digitization from IF or RF using an LC bandpass ΔΣ modulator avoids the traditional problems of direct-conversion receivers, such as EVM degradation due to IQ imbalance, 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>nd</sup> -order intermodulation, and AGC interaction with DC offset correction settling. Our target application is a low-power IEEE 802.11n receiver for 2.4 to 2.5GHz using a fixed 3.2GHz clock and IF tuned from 700 to 800MHz. The fixed clock allows an integer-N PLL with high reference frequency (40MHz, for example), which allows wide loop bandwidth and low phase noise, even at mW-level power consumption (e.g. [1]). The power savings from simplified LO generation are also important. Sampling from IF with an f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>s</sub> /4 modulator rather than sampling from RF with a 3f <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>s</sub> /4 modulator (as in [2]) gives higher ADC SNR because Q-enhanced LC filters have a tradeoff between Q and SNR and the loop filter fractional bandwidth is greater at the lower center frequency." @default.
- W2000966589 created "2016-06-24" @default.
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- W2000966589 date "2012-02-01" @default.
- W2000966589 modified "2023-09-24" @default.
- W2000966589 title "An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs" @default.
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- W2000966589 doi "https://doi.org/10.1109/isscc.2012.6176901" @default.
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