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• W2000976944 abstract "In this paper, the primitive common-multiplicand Montgomery modular multiplication is developed for modular exponentiation. Together with Montgomery powering ladder, a fast, compact and symmetric modular exponentiation architecture is proposed for hardware implementation. The architecture consists of one group of processing elements along the central line and two symmetric groups of accumulation units on two sides. The central elements perform modular reductions, while the symmetric units on both sides accumulate the modular multiplication results. A feedforwarding architecture is employed to decrease the latency between processing elements, in parallel with the word-based accumulation units, which are also pipelined. Meanwhile, due to the symmetric architecture and Montgomery powering ladder, the modular exponentiation is immune from fault and simple power attacks. Implemented in FPGA platform, the performance of our proposed design outperforms most results so far in the literature." @default.
• W2000976944 created "2016-06-24" @default.
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• W2000976944 date "2013-09-01" @default.
• W2000976944 modified "2023-09-23" @default.
• W2000976944 title "Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications" @default.
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• W2000976944 doi "https://doi.org/10.1016/j.vlsi.2012.09.002" @default.
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