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- W2001110521 abstract "Using new techniques it is possible to construct an EOS/ESD equivalent circuit of a product. Location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique. Rules for predicting location of ESD dissipation are defined. N+-P-N+ structures and n-channel transistors suffer from a current lock-on effect, which is apparently caused by a runaway oxide trapping mechanism. Different failure mechanisms are observed at narrow and wide pulse widths. Hot electron induced damage occurs under mechanical handling conditions. On CMOS outputs the n-channel device absorbs most of the ESD, and is very fragile." @default.
- W2001110521 created "2016-06-24" @default.
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- W2001110521 date "1985-03-01" @default.
- W2001110521 modified "2023-10-05" @default.
- W2001110521 title "ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms" @default.
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- W2001110521 doi "https://doi.org/10.1109/irps.1985.362100" @default.
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