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- W2001288892 abstract "We have designed CMOS polycells with a uniform height for LSI random logic circuits. The design objective was to minimize the product of propagation delay and chip area while allowing noise margins to be at least 25 percent of <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>V_{dd}</tex> . Designable parameters were identified to be channel widths in <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>p</tex> -type and <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</tex> -type transistors. Analytical models were derived to show the existence of an optimal solution point. Physical interpretations of models were also given. SPICE was used to simulate propagation delays and noise margins in inverter (INR), 2- and 3-input NAND and NOR gates under worst-case conditions. The chip performance of polycell-based CMOS circuits was then estimated by averaging performances of these five logic gates. With <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3.5-{mu}m</tex> design rules, the channel widths in <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>p</tex> -channel and <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</tex> -channel transistors were designed to be <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>35{mu}m</tex> and <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>17{mu}m</tex> , respectively." @default.
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- W2001288892 date "1981-08-01" @default.
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- W2001288892 title "A design of CMOS polycell for LSI circuits" @default.
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