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- W2001885526 abstract "This paper proposes an area-saving dual-path loop filter (LPF) for low-voltage integrated phase-locked loops (PLLs). With this LPF, output current of the lowpass-path charge-pump (CP) is B times (B > 1) as great as that of the integration-path CP. By adding voltages across these two paths, the zero-capacitance is magnified B times equivalently. As a result, the chip size is greatly reduced. Based on this LPF, a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18 μm RFCMOS technology. Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that, at a frequency of 3.20 GHz, phase noise is –120.2 dBc/Hz at 1 MHz offset, reference spur is –72 dBc, and power is 24 mW." @default.
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- W2001885526 date "2009-10-01" @default.
- W2001885526 modified "2023-09-27" @default.
- W2001885526 title "An area-saving dual-path loop filter for low-voltage integrated phase-locked loops" @default.
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- W2001885526 doi "https://doi.org/10.1088/1674-4926/30/10/105011" @default.
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