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- W2002136382 abstract "Real-time traffic classification is becoming increasingly critical for network management, traffic engineering, and network security. Current software-based solutions, however, have difficulties dealing with a great number of flows in today's high-speed networks. This paper proposes RocketTC, a scalable FPGA-based architecture, to accelerate traffic classification while maintaining high accuracy. It combines two significant elements: (1) an efficient flow management scheme using on-chip BRAMs for storing the flow table, and (2) a parallel and pipelined classification engine array with partial dynamic reconfiguration (PDR) on FPGA. We have implemented and evaluated RocketTC on Xilinx Virtex-5 FPGA based platform. Our results show a sustained throughput of over 20 Gbps for minimum packet size of 40 bytes, and high accuracy above 97% for classifying nearly a hundred popular applications. Additionally, it is easy for RocketTC to update more application types." @default.
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- W2002136382 date "2012-01-01" @default.
- W2002136382 modified "2023-09-28" @default.
- W2002136382 title "RocketTC: A high throughput traffic classification architecture" @default.
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- W2002136382 doi "https://doi.org/10.1109/iccnc.2012.6167454" @default.
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