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- W2002144471 abstract "A design of Java coprocessor used in IC bank card is presented in this paper. A 4Kb true dual port SRAM is used for stack to reduce data hazard. Two stack top registers keep same data with the top of stack, which can build a bypass that can handle the data hazard of pipeline. This Java coprocessor can execute 88 Java card instructions, with a size of 8185 gates at a clock of 125MHz." @default.
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- W2002144471 date "2014-10-01" @default.
- W2002144471 modified "2023-09-27" @default.
- W2002144471 title "A NOVEL JAVA COPROCESSOR with data hazard handling on FPGA for IC bank card" @default.
- W2002144471 doi "https://doi.org/10.1109/icsict.2014.7021163" @default.
- W2002144471 hasPublicationYear "2014" @default.
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