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- W2002187871 abstract "A delay matrix and a gradual switching of shunt capacitors in delay cells are proposed for a wide-range-locking multi-phase DLL. With an interpolating resistor network, delay step error is greatly reduced by error averaging. The DLL, implemented in 0.13mum CMOS, has a locking range of 40 to 800MHz. With 40 phases, the maximum delay step error is 16.7ps at 700MHz. The chip dissipates 43mW at 700MHz from a 1.2V supply and the measured jitter is 12pspp and 1.6psrms." @default.
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- W2002187871 date "2007-02-01" @default.
- W2002187871 modified "2023-09-27" @default.
- W2002187871 title "A 40-to-800MHz Locking Multi-Phase DLL" @default.
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- W2002187871 doi "https://doi.org/10.1109/isscc.2007.373416" @default.
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