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• W2002255493 abstract "We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays." @default.
• W2002255493 created "2016-06-24" @default.
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• W2002255493 date "2014-07-28" @default.
• W2002255493 modified "2023-10-14" @default.
• W2002255493 title "Ion traps fabricated in a CMOS foundry" @default.
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• W2002255493 doi "https://doi.org/10.1063/1.4892061" @default.
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