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- W2003221521 abstract "In this paper a high-throughput FPGA implementation of a Volterra-based Decision Feedback Equalizer (DFE) is presented for first time. The DFE is a popular scheme, and its performance is a critical issue in high-speed communication systems. To overcome the throughput limitation due to the feedback loop, two multiplexer-based architectures were developed and compared. The introduced architectures were implemented on two Xilinx FPGAs, exploiting the specific features of these devices. Based on the experimental results, it is proved that the introduced designs achieve high throughput (10Gb/s), showing that the FPGAs are a suitable option for high-speed systems (e.g. optical communication systems)." @default.
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- W2003221521 date "2014-10-02" @default.
- W2003221521 modified "2023-09-24" @default.
- W2003221521 title "FPGA Implementations for Volterra DFEs" @default.
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- W2003221521 doi "https://doi.org/10.1145/2645791.2645831" @default.
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