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- W2003235155 abstract "A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-㎚ CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9?28 inch Nelco4000-6 microstrips at 4?7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 ㎟ and consumes 69.8 ㎽, while the rest of the receiver occupies 0.297 ㎟ and consumes 56.0 ㎽ at the 7-Gb/s data-rate and supply voltage of 1.35 V." @default.
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- W2003235155 date "2012-12-30" @default.
- W2003235155 modified "2023-09-23" @default.
- W2003235155 title "A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring" @default.
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- W2003235155 doi "https://doi.org/10.5573/jsts.2012.12.4.433" @default.
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