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- W2003249161 abstract "As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead." @default.
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- W2003249161 date "2014-02-01" @default.
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- W2003249161 title "Measurements of Process Variability in 40-nm Regular and Nonregular Layouts" @default.
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- W2003249161 doi "https://doi.org/10.1109/ted.2013.2294742" @default.
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