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- W2003358164 abstract "This paper presents a loadless CMOS four-transistor (4T) cell for very high density embedded SRAM applications. Using 0.18-/spl mu/m CMOS technology, the memory cell size is 1.9344 /spl mu/m/sup 2/ (1.04 /spl mu/m/spl times/1.86 /spl mu/m), which is 35% smaller than a six-transistor (6T) cell using the same design rule. The newly developed CMOS 4T-SRAM cell operates with high stability at 1.8 V, even though its designed cell ratio is 1.0 to minimize the area. A pair of pMOS transfer transistors is used to store and retain full-swing signals in the cell without a refresh cycle. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load." @default.
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- W2003358164 date "2001-01-01" @default.
- W2003358164 modified "2023-10-10" @default.
- W2003358164 title "A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology" @default.
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- W2003358164 doi "https://doi.org/10.1109/16.974716" @default.
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