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• W2003444784 abstract "We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth." @default.
• W2003444784 created "2016-06-24" @default.
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• W2003444784 date "2012-01-01" @default.
• W2003444784 modified "2023-09-30" @default.
• W2003444784 title "A 0.013 ${hbox {mm}}^{2}$, 5 $muhbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply" @default.
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• W2003444784 doi "https://doi.org/10.1109/jssc.2011.2163552" @default.
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