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- W2003579375 abstract "Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars. Main technology constraint is formation of narrow pillars with high aspect ratio and charge imbalance in these pillars. We propose a method to obtain high breakdown voltage in planar SJ-LDMOS by reducing the effect of charge imbalance at the drain end without reducing width of the pillars and no significant change in I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ON</sub> . The breakdown voltage of 120 V in a HV CMOS technology with tox of 13nm is achieved without ION degradation, as compared to 100 V conventional LDMOS device." @default.
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- W2003579375 date "2013-06-01" @default.
- W2003579375 modified "2023-09-26" @default.
- W2003579375 title "120 V super junction LDMOS transistor" @default.
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- W2003579375 doi "https://doi.org/10.1109/edssc.2013.6628135" @default.
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