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- W2003758461 abstract "Recently bit sequential multiplier algorithms have been found more useful in the area of interconnection of multiple processors within a VLSI structure [1], [2]. The object of the present paper is to suggest modified bit sequential algorithms to achieve more speed and to attain its conformity with other algorithms such as division, square-rooting etc. with a view to utilize them in future arithmatic arrays. In the present paper the following has been taken up: a) Bit sequential multiplier using carry look-ahead technique, b) Bit sequential multiplier using most significant bit first, and c) Negabinary bit sequential multiplier" @default.
- W2003758461 created "2016-06-24" @default.
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- W2003758461 date "1983-06-01" @default.
- W2003758461 modified "2023-09-26" @default.
- W2003758461 title "On bit sequential multipliers" @default.
- W2003758461 cites W1974307748 @default.
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- W2003758461 doi "https://doi.org/10.1109/arith.1983.6158075" @default.
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