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- W2004144979 abstract "Editor's note:High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs.—Andres Takach, Mentor Graphics" @default.
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- W2004144979 date "2009-07-01" @default.
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- W2004144979 title "Functional Equivalence Verification Tools in High-Level Synthesis Flows" @default.
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- W2004144979 doi "https://doi.org/10.1109/mdt.2009.79" @default.
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