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- W2004297226 abstract "This paper presents a research on arithmetic units targeted to implement model predictive control (MPC) in a custom embedded processor. A novel hardware implementation of cotransformation for the calculation of addition and subtraction in the Logarithmic Number System (LNS) is proposed. This architecture provides a small ROM-less adder/subtracter, with longer operation latency than other LNS techniques, but easily pipelineable. These characteristics make it very adequate for implementing the datapath of custom MPC embeddable microprocessors. A review of the arithmetic customization process is presented, including: an analysis of the finite precision problem, modifications to the standard MPC algorithm that simplify embedding the application, and the reasons that suggest better performance of LNS over standard floating-point (FP) architectures. The proposed arithmetic unit architecture for 16-bit LNS is fully synthesized for ASIC, and compared with an equivalent FP implementation. Area and clock cycle estimates are compared. Finally, considerations on low-precision implementations of LNS arithmetic units are provided, and an embedded-ROM implementation of addition/subtraction in LNS is proposed and analyzed." @default.
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- W2004297226 date "2004-09-22" @default.
- W2004297226 modified "2023-09-23" @default.
- W2004297226 title "LNS architectures for embedded model predictive control processors" @default.
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- W2004297226 doi "https://doi.org/10.1145/1023833.1023845" @default.
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