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- W2004359925 abstract "We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the- art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favorably comparable to the JPEG baseline lossless image compression schemes. We also discuss the parallelization issues of the JPEG baseline standard still compression schemes and their difficulties." @default.
- W2004359925 created "2016-06-24" @default.
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- W2004359925 date "1994-05-02" @default.
- W2004359925 modified "2023-09-23" @default.
- W2004359925 title "<title>Parallel butterfly algorithm and VLSI architectures for image decorrelation</title>" @default.
- W2004359925 doi "https://doi.org/10.1117/12.174967" @default.
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