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• W2004458344 abstract "We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The use of the internal scan chain for decompression obviates the need for a CSR. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS 89 benchmark circuits." @default.
• W2004458344 created "2016-06-24" @default.
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• W2004458344 date "2001-03-13" @default.
• W2004458344 modified "2023-09-26" @default.
• W2004458344 title "Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding" @default.
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• W2004458344 doi "https://doi.org/10.5555/367072.367125" @default.
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