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• W2004695592 abstract "For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques." @default.
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• W2004695592 date "2010-01-01" @default.
• W2004695592 modified "2023-10-16" @default.
• W2004695592 title "Static Address Generation Easing: a design methodology for parallel interleaver architectures" @default.
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• W2004695592 doi "https://doi.org/10.1109/icassp.2010.5495535" @default.
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