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- W2004752093 abstract "An efficient analytical method for calculating the propagation delay and the short-circuit power dissipation of CMOS gates is introduced in this paper. Key factors that determine the operation of a gate, such as the different modes of operation of serially connected transistors, the starting point of conduction, the parasitic behaviour of the short-circuiting block of a gate and the behaviour of parallel transistor structures are analysed and properly modelled. The analysis is performed taking into account second-order effects of short-channel devices and for non-zero transition time inputs. Analytical expressions for the output waveform, the propagation delay and the short-circuit power dissipation are obtained by solving the differential equations that govern the operation of the gate. The calculated results are in excellent agreement with SPICE simulations. Copyright © 1999 John Wiley & Sons, Ltd." @default.
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- W2004752093 title "Analytical estimation of propagation delay and short-circuit power dissipation in CMOS gates" @default.
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- W2004752093 doi "https://doi.org/10.1002/(sici)1097-007x(199907/08)27:4<375::aid-cta64>3.0.co;2-7" @default.
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