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- W2004850003 abstract "This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge1−xCx/Si p-MOSFETs. The silicon-cap thickness (3–9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and Ion–Ioff ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge1−xCx interface was quantitatively extracted by fitting the stair-case behavior of split C–V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations." @default.
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- W2004850003 date "2010-02-16" @default.
- W2004850003 modified "2023-09-27" @default.
- W2004850003 title "Effects of Si-cap thickness and temperature on device performance of Si/Ge1−xCx/Si p-MOSFETs" @default.
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- W2004850003 doi "https://doi.org/10.1088/0268-1242/25/4/045005" @default.
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