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• W2004966407 abstract "Abstract-The combination of tetragonal ZrO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> (t-ZrO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> ) and amorphous Al <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> O <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> was explored as the gate dielectric for Si-based MOS devices. Because of the absence of a ZrSiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>4</sub> and/or ZrSi interfacial layer, the thermally stable t-ZrO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> /Al <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> O <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> /Si stack is more eligible than the Al <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> O <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> /t-ZrO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> /Si stack for the gate dielectric since it demonstrates larger capacitance, smaller hysteresis, better frequency dispersion, lower leakage current, and more robust reliability. By employing additional NH <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> plasma nitridation to well passivate the grain boundaries of the t-ZrO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> film, without compromising its κ-value, a greatly reduced leakage current of 2.9 × 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-8</sup> A/cm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> can be achieved at gate bias of flatband voltage (V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>fb</sub> )-1 V with an effective oxide thickness of 1.64 nm, which paves a new way to develop a high-performance crystalline gate dielectric for advanced MOS devices." @default.
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• W2004966407 date "2010-09-01" @default.
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• W2004966407 title "Tetragonal $hbox{ZrO}_{2}/hbox{Al}_{2}hbox{O}_{3}$ Stack as High-$kappa$ Gate Dielectric for Si-Based MOS Devices" @default.
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• W2004966407 doi "https://doi.org/10.1109/led.2010.2053191" @default.
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