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• W2005156956 abstract "This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</sub> , without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>MIN</sub> ). Single-ended write is accomplished in two phases using dual word-lines. Finally, we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing, for the same bitcell area." @default.
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• W2005156956 date "2010-03-01" @default.
• W2005156956 modified "2023-09-23" @default.
• W2005156956 title "Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation" @default.
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• W2005156956 doi "https://doi.org/10.1109/isqed.2010.5450400" @default.
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