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- W2005236102 abstract "As interconnect densities increase with each technology generation, the lithographic processes required to printall features with acceptable irregularities have become more complex. Restricted design rules (RDR) and modelbasedDesign for Manufacturability (DFM) guidelines have been added to the existing Design Rule Check (DRC)software to prevent unprintable patterns to be drawn on the mask by predicting their imprint on the wafer. Itis evident from analyses of predicted patterns that edge placement errors have a continuous distribution, hencea pass/fail cut-off is somewhat arbitrary. In this paper, we describe a methodology to perform StatisticalLithography Rules Check (Stat-LRC) involving design yield based on interconnect linewidth distribution forvariation in lithographic input error sources. In this scheme, a list of error locations indicating polygons thathave yield below a user specified threshold are listed. The overall design yield is recovered by trading-off slightly poorer EPE distributions for lines with short runs with excellent ones. The simulation/analysis environment is fully automated and yield recovery improvement has been demonstrated." @default.
- W2005236102 created "2016-06-24" @default.
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- W2005236102 date "2010-03-11" @default.
- W2005236102 modified "2023-09-23" @default.
- W2005236102 title "Stat-LRC: statistical rules check for variational lithography" @default.
- W2005236102 doi "https://doi.org/10.1117/12.846606" @default.
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