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- W2005285417 abstract "This paper presents the design and study of an architecture able to perform 10 Gbit/s GFP frame delineation with single bit error correction on an FPGA. The design targets the development of a system-on-chip (SoC) platform for the design of next generation network processing. In order to achieve the high processing rate, the circuit is designed with a 64-bit data-path and is targeted to Altera Stratix II FPGA technology. The circuit operates at a clock rate of 165 MHz. The circuit utilises 8 parallel CRC HEC calculators and comparators, a PLI frame counter and a single bit error correction mechanism." @default.
- W2005285417 created "2016-06-24" @default.
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- W2005285417 date "2005-01-01" @default.
- W2005285417 modified "2023-09-27" @default.
- W2005285417 title "A 10 Gbps GFP frame delineation circuit with single bit error correction on an FPGA" @default.
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- W2005285417 doi "https://doi.org/10.1109/aict.2005.1" @default.
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