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- W2005333634 abstract "Expressions are derived for minimum propagation-delay time and DC operational conditions in the I/SUP 2/L circuit configuration, and are applied to several kinds of I/SUP 2/L limitations. 1) Ultimately achievable (roughly 0.34 ns, fan-out of 2) and reasonably expected minimum propagation-delay values (0.75-1.0 ns considering simple n-p-n limitations) are estimated. 2) Speed improvements of the standard I/SUP 2/L structure via doping level adjustment is shown to be minimal (it is primarily useful for ensurance of DC operation). 3) Requiring analog compatibility further constrains performance; a figure of merit of about 1 to 2 V/ns is derived and experimentally confirmed for the product of analog device BV/SUB CBO/ and I/SUP 2/L speed for standard epitaxial I/SUP 2/L processing. Radical techniques using dual buried layers, dual epitaxial layers, or Poly I/SUP 2/L offer considerably enhanced performance by attacking the parameter with primary leverage on these tradeoffs: base-to-buried layer spacing W/SUB epi/. Analysis of Poly I/SUP 2/L reveals specific advantages." @default.
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- W2005333634 date "1979-10-01" @default.
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- W2005333634 title "Considerations for high-speed and analog-circuit-compatible I/sup 2/L and the analysis of Poly I/sup 2/L" @default.
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- W2005333634 doi "https://doi.org/10.1109/jssc.1979.1051289" @default.
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