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- W2005442712 abstract "CMOS device improvements have recently been achieved by changing the geometry of the device from planar to fully-depleted (FD) FinFET. Also FD SOI (Silicon-on-Isolator) devices have emerged as a candidate for replacing bulk silicon in ULSI applications in future technology nodes. Along with this scaling comes, however, a challenging penalty: device self-heating. In this study, i) we propose a unique measurement technique for self-heating and use it to assess self-heating in planar devices, ii) we compare and verify these results with finite-element simulations and iii) we provide perspectives for upcoming FinFET nodes." @default.
- W2005442712 created "2016-06-24" @default.
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- W2005442712 date "2014-06-01" @default.
- W2005442712 modified "2023-10-01" @default.
- W2005442712 title "Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes" @default.
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- W2005442712 doi "https://doi.org/10.1109/irps.2014.6861186" @default.
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