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Matches in SemOpenAlex for { <https://semopenalex.org/work/W2005778825> ?p ?o ?g. }

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• W2005778825 abstract "This work presents a computer architectural approach at identifying sources of inefficiency in a typical 5-stage pipelined, general purpose soft processor implementation on a modern FPGA. The analysis starts with a naive implementation of the processor which focuses on correctness, modularity, and speed of development. It then extracts a list of components and mechanisms in the processor pipeline as sources of inefficiency. A designer would have to cleverly redesign these components in order to improve the processor's operating clock frequency. Using the results of this analysis, this work proposes various optimizations to improve the efficiency of such components. The optimizations increase the processor clock frequency from 145MHz to 281MHz on Stratix III devices, while overall instruction processing throughput increases by 80%." @default.
• W2005778825 created "2016-06-24" @default.
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• W2005778825 date "2014-05-11" @default.
• W2005778825 modified "2023-09-22" @default.
• W2005778825 title "An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design" @default.
• W2005778825 hasPublicationYear "2014" @default.
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