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- W2005809747 abstract "This paper presents a phase-locked loop (PLL) for a clock generator in data communication system. The PLL exhibits simultaneously low jitter and low power consumption. Fully integrated loop filter simplifies the peripheral circuit. It has been fabricated using a 0.35 µm BiCMOS process, occupying 0.07 mm2 of silicon area. For a 50 MHz output frequency, the circuit features a 119 ps peak-to-peak jitter. At that frequency, the PLL consumes less than 6mW from a supply voltage of 3.3 V. The clock generator has been successfully applied in a receiver." @default.
- W2005809747 created "2016-06-24" @default.
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- W2005809747 date "2010-11-01" @default.
- W2005809747 modified "2023-09-23" @default.
- W2005809747 title "A low-jitter and low-power clock generator" @default.
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- W2005809747 doi "https://doi.org/10.1109/icsict.2010.5667706" @default.
- W2005809747 hasPublicationYear "2010" @default.
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