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- W2006288420 abstract "A new architecture for configurable blocks is proposed which can be used to construct multipliers. An array of these blocks is capable of being configured to perform any 4m bit × 4n bit signed/unsigned binary multiplication. The blocks are designed to be embedded within a conventional FPGA structure to increase the functionality of the device by freeing valuable general reconfigurable resources, particularly when used in the area of image processing." @default.
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- W2006288420 date "1998-01-01" @default.
- W2006288420 modified "2023-10-18" @default.
- W2006288420 title "Configurable multiplier blocks for embedding in FPGAs" @default.
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- W2006288420 doi "https://doi.org/10.1049/el:19980501" @default.
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