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• W2006309616 abstract "The typical mold method for FED fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by low pressure chemical vapor deposition (LPCVD), and then boro phospher silicate glass (BPSG) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed." @default.
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• W2006309616 date "2003-04-01" @default.
• W2006309616 modified "2023-10-03" @default.
• W2006309616 title "Fabrication of field emitter arrays using the mold method for FED application" @default.
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• W2006309616 doi "https://doi.org/10.1016/s0038-1101(02)00315-5" @default.
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