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- W2006455512 abstract "A novel, very high-performance fuzzy logic processor architecture has been developed and conceptually proven. Processing of over 1.2 billion fuzzy logic instructions per second is possible. It is an 8-bit, fully parallel, synchronous, pipelined employing max-min based rule inferencing. The concept has been proven using complex programmable logic devices (CPLDs), exploiting both the high gate count and I/O pin count, as well as the reconfigurable structure. True non-singleton center-of-gravity defuzzification has also been developed incorporating an optimized dividing speeds significantly greater than the currently available commercial deices. Implementation in CPLDs allows reconfigurability in the fuzzy logic design, while custom devices allow a much greater degree of integration and potential for even greater processing speeds. High speed fuzzy logic processing is particularly suited to high bandwidth data processing applications such as virtual reality.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only." @default.
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- W2006455512 title "<title>Fully parallel fuzzy logic processor architecture: exceeding one billion rules per second</title>" @default.
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