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• W2007066032 abstract "We propose new accurate predictive models for the delay, power, and area of buffered interconnects to enable a more effective system-level design exploration with existing and future nanometer technology processes. We show that our models are significantly more accurate than previous models - essentially matching sign-off analyses. We integrate our models in the COSI-OCC communication synthesis infrastructure and show how they impact the feasibility and optimality of the network-on-chip architectures that are synthesized by this tool." @default.
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• W2007066032 date "2010-04-01" @default.
• W2007066032 modified "2023-10-16" @default.
• W2007066032 title "Accurate Predictive Interconnect Modeling for System-Level Design" @default.
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• W2007066032 doi "https://doi.org/10.1109/tvlsi.2009.2014772" @default.
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