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• W2007309178 abstract "In this paper, a 60-GHz high gain low-noise amplifier is designed and verified experimentally. Firstly, inductors with asymmetrical ground plane are introduced and studied by using EM simulation, obtains an improvement of quality-factor. Then, a three-stage cascade low-noise amplifier using the proposed inductors is designed. Fabricated in Global Foundries 65-nm CMOS process, the low-noise amplifier features a peak gain of 26.3 dB with 21.8 mW DC power consumption, a noise figure of 5.3 dB, an average output P <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>1dB</sub> of -4 dBm, and a core size of 0.15 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . In the comparison with prior arts, the proposed design achieves the highest gain and figure-of-merit." @default.
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• W2007309178 date "2014-08-01" @default.
• W2007309178 modified "2023-09-27" @default.
• W2007309178 title "A 60-GHz 26.3-dB gain 5.3-dB NF low-noise amplifier in 65-nm CMOS using Q-factor enhanced inductors" @default.
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• W2007309178 doi "https://doi.org/10.1109/ursigass.2014.6929462" @default.
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