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• W2007508500 abstract "Multiprocessors are becoming a common type of modern computers. In this work, we focus on the bus architecture, in which a shared bus is used for communication between processors — and between processors and memories. We consider the following optimization problem. Assume that k processors access m memory banks through a single bus. In order to fulfill an access request for bank i, the bus has to be connected to that bank; the bus can be connected at any time to at most one bank of memory. The cost of servicing a request to access bank i, 1≤i ≤m, is λ, if the bus is connected to bank i, and μ, if the bus is connected to some bank j≠i; in this case μ−λ>0 is a setup cost, or the cost of switching the bus from bank j to bank i. Given a sequence of memory access requests, we need to determine the order by which the requests will be serviced, so as to minimize one of the following objective functions: (i) makespan: the overall time until all the requests in the sequence have been completed, (ii) total completion time (TCT): sum of the completion times of all the processors, (iii) maximum response time: the maximal time that elapses between services of consecutive requests of processor i, 1≤i≤k. Using the k-client model, introduced by Alborzi et al. (1997), we study algorithms that schedule accesses to the memory banks in an offline and online fashion. In the offline case we show, that using dynamic programming our problem can be solved optimally for a large set of instances, for each of the above objective functions. For general inputs we give approximation algorithms, for the makespan and the TCT measures. In the online case, we show a lower bound of Ω(μ/λ) on the competitive ratio of any deterministic algorithm, for each of the above measures. We also show that the bound is tight for all measures, by describing algorithms whose competitive ratios are O(μ/λ). Finally, we examine the performance of the algorithms studied in this work in real system environment, via simulation experiments." @default.
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• W2007508500 date "2001-10-01" @default.
• W2007508500 modified "2023-10-14" @default.
• W2007508500 title "Scheduling memory accesses through a shared bus" @default.
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• W2007508500 doi "https://doi.org/10.1016/s0166-5316(01)00050-5" @default.
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