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• W2007673487 abstract "The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process." @default.
• W2007673487 created "2016-06-24" @default.
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• W2007673487 date "2014-02-19" @default.
• W2007673487 modified "2023-09-26" @default.
• W2007673487 title "Source-side injection single-polysilicon split-gate flash memory" @default.
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• W2007673487 doi "https://doi.org/10.7567/jjap.53.034201" @default.
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