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- W2008416958 abstract "Short channel effects in double gate poly-Si SLS ELA TFTs are studied in this work by electrically characterizing devices with varying top gate length and constant bottom gate length. The electrical parameters were extracted for different bottom gate biases, observing a V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>th</sub> increase with increasing channel length, attributed to more traps present within larger channels. This was also probed through the increase of V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>g,max</sub> -V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>th</sub> with increasing channel length. In order to distinguish between short channel effects and possible L <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>top</sub> /L <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>bottom</sub> effects, devices with different bottom gate lengths and a constant top gate length were also studied. No similar trends as in the case of decreasing channel length were observed, thus supporting our case that the previously observed behavior is mainly an effect of channel shrinking and not of L <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>top</sub> /L <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>bottom</sub> effects." @default.
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- W2008416958 date "2012-05-01" @default.
- W2008416958 modified "2023-10-17" @default.
- W2008416958 title "Short channel effects in double gate polycrystalline silicon SLS ELA TFTs" @default.
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- W2008416958 doi "https://doi.org/10.1109/miel.2012.6222804" @default.
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