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- W2008436714 abstract "In this paper, we describe VLSI implementation using a new vision chip architecture that enables various visual processings on the same architecture and combines high speed and the high accumulation. A 64 × 64 pixel prototype vision chip and its evaluation results are shown. The chip is integrated on a 3.6 mm × 3.9 mm chip using a 0.35 μm CMOS DLP/TLM process; the pixel size is 33.0 μm × 33.0 μm. The maximum current consumption is approximately 500 mA." @default.
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- W2008436714 date "2006-09-01" @default.
- W2008436714 modified "2023-10-05" @default.
- W2008436714 title "Development of High-resolution Digital Vision Chip Based on CFPE Architecture" @default.
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- W2008436714 doi "https://doi.org/10.1109/camp.2007.4350344" @default.
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