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- W2008702493 abstract "This paper describes a new algorithm that automatically generates tub regions for VLSI symbolic layouts with quality comparable to that of human designers. The algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. In addition, the algorithm runs at O(n/sup 2/) time and O(n) space with the expected run time of O(n log n)." @default.
- W2008702493 created "2016-06-24" @default.
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- W2008702493 date "1989-01-01" @default.
- W2008702493 modified "2023-09-26" @default.
- W2008702493 title "Automatic tub region generation for symbolic layout compaction" @default.
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- W2008702493 doi "https://doi.org/10.1145/74382.74433" @default.
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